Inexpensive personal computers (PC's) commonly use digital-audio systems. Audio inputs may be sampled at a rate of 11.025, 22.05, or 44.1 KHz, or at rates of 8, 16, 32, or 48 KHz. These audio samples are often stored and altered in a PC before being played back, often at a different rate.
It may be desired to play back an audio sample at a different rate, or to mix audio samples having different sample rates. One of the audio samples must be converted to the sample rate of the other audio sample for mixing or playback to occur. Sample-rate conversion software or hardware is used to convert the sample rate.
While many approaches to sample-rate conversion are used, satisfactory results are not always achieved. The human ear is quite sensitive to slight distortions or discontinuities of a sound. Coarse sample-rate conversion produces noticeable distortion.
A particular problem occurs when audio streams are synchronized to independent free-running clocks. The clocks for the two audio streams may be generated from two different crystal oscillators. Even when the frequencies are the same, slight differences can occur between the two crystals. The frequency difference may be up to 1000 parts-per-million (ppm). For a nominal 11,025 Hz sample rate, the frequency can be as high as 11025+11.025 or 11036 Hz. When a 11036 Hz audio signal synchronized to one crystal oscillator is converted to a 11025 Hz rate, audio samples may be deleted after every thousand or so samples. Deleting audio samples can cause audible clicks or pops.
Analog SRC--FIG. 1
FIG. 1 shows a prior-art sample-rate conversion using a pair of digital-analog converters. An input audio stream was sampled at frequency f0, and has samples x(0), x(1), . . . x(m). Each sample is a multi-bit binary number representing the intensity of the sound at a point in time; 16-bit binary numbers in two's complement are commonly used for each sample. The input sample at frequency f0 is to be converted to the output audio stream having a sample rate of f1, with samples y(0), y(1), . . . y(n). The number of sample points in the input stream, m, often differs from the number of samples in the output stream, n. The ratio of the number of samples, m/n, is equal to the frequency ratio f0/f1. The converted audio stream must have the same total play time, even though the number of samples increases or decreases and the rate of sample play back likewise increases of decreases.
The digital input samples x(i) are converted to analog voltages on line 6 by digital-to-analog converter (DAC) 8. DAC 8 converts an input sample for each period of input clock 16, which operates at input frequency f0. The capacitance on line 6 maintains the voltage generated by DAC 8 until the next sample is converted.
The voltage on line 6 is sampled by analog-to-digital converter (ADC) 10, which generates a digital value representing the voltage sampled from line 6. This digital value is output as output sample y(i). ADC 10 samples the voltage on line 6 for each period of output clock 15, which operates at output frequency f1.
While such an analog sample converter may be considered exact, since DAC 8 and ADC 10 operate from independent clocks 15, 16, it is complex and expensive. The analog circuits are difficult to integrate with other digital circuits on a VLSI integrated circuit (IC). Also, the quality of the digital audio stream is degraded by the multiple analog-digital conversions.
FIFO with SRC--FIGS. 2, 3
FIG. 2 illustrates using a FIFO to buffer a sample-rate converter. First-in-first-out FIFO 12 is written with an input audio sample x(i) for each pulse of the input clock 16, which operates at input frequency f0. Sample-rate converter 14 is an all-digital converter that reads digital samples from FIFO 12 and outputs digital samples at the output frequency f1 in response to output clock 15. Sample-rate converter 14 generates derived clock 18 from output clock 15 by multiplying the output clock by Q and dividing by P. Thus derived clock 18 has a derived frequency f2 of (Q/P)*f1. Q and P are chosen so that f2 is about the same as input frequency f0. Thus FIFO 12 is read and written at about the same frequency.
When Q/P is not exactly the ratio of f0 to f1, FIFO 12 is read and written at slightly different rates. FIFO 12 can fill up or become empty. Samples can over-write earlier samples, or random or null data can be output as a sample. Thus simply using a FIFO can produce undesirable audio noise.
FIG. 3 shows using read and write pointers to control the FIFO buffering a sample-rate converter. Write counter 24 is clocked by input clock 16 while read counter 26 is clocked by derived clock 18. Thus write counter 24 keeps track of the write location in FIFO 12 while read counter 26 indicates the reading location in FIFO 12. Comparator 28 compares the values of write counter 24 and read counter 26 to determine when FIFO 12 is full or empty.
When write counter 24 matches read counter 26, FIFO 12 has become empty, and signal 30 causes FIFO 12 to continue to output the last audio sample, effectively duplicating an audio sample. When write counter 24 is ahead of read counter 26 by the size of FIFO 12, then comparator 28 detects that FIFO 12 is full. Input samples are prevented from being written into FIFO 12 until one or more samples have been read out to sample-rate converter 14. This essentially drops an audio sample.
Audible distortions can occur when FIFO 12 fills, since an input sample must be skipped rather than written to the full FIFO. When FIFO 12 becomes empty, a sample is missing and a previous sample may need to be duplicated, or a null or random sample output. While this is superior to simply allowing FIFO 12 to over-run or under-run, audible clicks or pops may still be discernable by the listener.
Phase Detector with SRC--FIG. 4
FIG. 4 highlights using a high-precision phase detector to alter the sampling ratio. This has been described by Julius O. Smith and Phil Gossett in "A Flexible Sampling-Rate-Conversion Method" at Stanford University. See also U.S. Pat. No. 5,398,029 by Toyama et al., and assigned to Nippon Precision Circuits Inc.
Sample-rate converter 14' is modified to vary the ratio Q/P in response to adjust signal 22 from phase detector 20. Phase detector 20 compares the instantaneous phase and frequency of input clock 16 to derived clock 18' generated by Sample-rate converter 14'. When the phase or frequency f0 varies from f2, phase detector 20 alters adjust signal 22. Sample-rate converter 14' responds to adjust signal 22 by increasing or decreasing the ratio Q/P, thus altering derived clock 18'. When derived clock 18' is adjusted sufficiently to match the phase and frequency of input clock 16, then adjust signal 22 stabilizes, causing sample-rate converter 14' to stop adjusting derived clock 18'. Changes in input clock 15 are thus tracked by sample-rate converter 14' in a similar manner to a Phase-locked loop (PLL).
Phase detector 20 is a high-precision detector running at a high frequency. Phase detector 20 must operate at a frequency at least 1000 times that of input frequency f0 so that phase changes of less than the clock period can be detected. Sample-rate converter 14' also needs a large memory for storing many sets of filter coefficients for the many possible ratios of Q/P.
What is desired is a digital sample-rate converter for common PC-audio sampling rates. It is desired to buffer digital-audio samples synchronized to independent clocks that may vary slightly in frequency. A digital sample-rate converter is desired that can eliminate audible clicks and pops caused by slight mismatches of sampling rates. A sample-rate converter with reduced coefficient storage is also desirable. High audio quality is desirable when samples from independent crystal oscillators are used.